1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and particularly to a semiconductor integrated circuit device including a substrate bias generating circuit.
2. Description of the Background Art
An example of a semiconductor integrated circuit device including a substrate bias generating circuit is a semiconductor memory of a CMOS structure.
The above described semiconductor integrated circuit device having a CMOS structure comprises a memory section and a peripheral circuit section. The memory section comprises a circuit formed on a P-type substrate and each node thereof has a PN junction. When the potential of the N layers of the PN junction is lowered due to undershoot of a signal inputted to the above described circuit, a forward bias voltage is applied to the above described PN junction, and a current which is not inherently to flow in the PN junction section actually flows, so that memory cell information, for example, is liable to be destroyed.
To prevent malfunctions of such an internal circuit, it has been proposed that the P-type substrate is provided with a negative potential to keep the PN junction section always in the reverse bias state. A substrate bias generating circuit is a circuit which is provided for supplying the negative potential therefor.
FIG. 1 illustrates a cross sectional structure of a conventional semiconductor integrated circuit device of a CMOS structure, including the above mentioned substrate bias generating circuit. In the semiconductor integrated circuit device shown in FIG. 1, a CMOS inverter is formed as shown by an equivalent circuit of FIG. 2. In FIG. 1, an N-type well 2 is formed in a P-type semiconductor substrate 1, and a P-channel MOS transistor PQ is formed within the N-type well 2. The P-channel MOS transistor PQ comprises P.sup.+ diffusion layers 3 and 4, a gate insulation film which is a region between these P.sup.+ diffusion layers 3 and 4 and formed on the surface of the N-type well 2, and a gate electrode 6 formed on this gate insulation film 5. Meanwhile, an N-channel MOS transistor NQ is formed in the other part of the P-type semiconductor substrate 1 where the N-type well 2 is not formed. The N- channel MOS transistor NQ comprises N.sup.+ diffusion layers 7 and 8 which are source and drain, respectively, a gate insulation film 9 which is a region between these N.sup.+ diffusion layers 7 and 8 and formed on the surface of the P-type semiconductor substrate 1, and a gate electrode 10 formed on the gate insulation film 9. The gate electrodes 6 and 10 are connected to an input terminal, while the P.sup.+ diffusion layer 3 and N.sup.+ diffusion layer 8 are connected to an output terminal Further, a supply voltage V.sub.CC is applied to the P.sup.+ diffusion layer 4 while a ground voltage V.sub.ss is applied to the N.sup.+ diffusion layer 7. The supply voltage V.sub.CC is also applied to the N-type well 2 through an N.sup.+ diffusion layer 11.
In the above described structure, a substrate bias generating circuit (hereinafter referred to as a V.sub.BB generating circuit) 12 is formed on the semiconductor substrate 1. The V.sub.BB generating circuit 12 generates a negative voltage when the supply voltage V.sub.CC is applied. This negative voltage is supplied to the semiconductor substrate 1. Accordingly, after a power supply is turned on, a region between the P-type semiconductor substrate 1 and the N layer contacting therewith is rendered reverse bias, so that the previously mentioned inconvenience is eliminated.
Meanwhile, upon feeding the supply voltage V.sub.CC, the potential of the P-type semiconductor substrate 1 is raised by a junction capacitance C between the P-type semiconductor substrate 1 and the N-type well 2. Furthermore, when the operation of the circuit in the semiconductor substrate is started by turning on of the power supply, an electric current flows in the semiconductor substrate to cause fluctuation of a substrate voltage. As a result, the substrate voltage is increased. However, when the supply voltage V.sub.CC is low, the V.sub.BB generating circuit 12 has relatively a low current driving capability, so that a rise in the potential of the semiconductor substrate 1 cannot be suppressed promptly. A thyristor circuit, in which P layers and N layers are alternately superimposed in four layers as shown in FIG. 3, is parasitic between the supply voltage V.sub.CC and the ground voltage V.sub.SS. If the potential of the semiconductor substrate 1 rises upon turning on of the power supply, a region between the semiconductor substrate 1 and the N.sup.+ diffusion layer 7 is rendered forward bias and the thyristor circuit shown in FIG. 3 is turned on. As a result, a current constantly flows through a path shown with a chain dotted line in FIG. 1. This phenomenon is called latch up, causing malfunctions of the circuit and destruction of the elements.
Circuits shown in FIGS. 4 and 7 have been proposed in order to prevent the latch up on turning on of the power supply as described above.
A conventional example shown in FIG. 4 comprises a V.sub.BB clamping circuit 13 in addition to the V.sub.BB generating circuit 12. This V.sub.BB clamping circuit 13 operates responsive to an output signal POR of a POR pulse generating circuit 14 and serves to clamp the substrate potential down to the ground potential until the driving capability of the V.sub.BB generating circuit 12 to reduce the substrate voltage is sufficiently high after the supply voltage is applied. The V.sub.BB clamping circuit 13 comprises two N-channel MOS transistors Q.sub.1 and Q.sub.2 and a capacitor C.sub.A. The transistor Q.sub.1 has its drain connected to a V.sub.SS line l2, its source connected to a V.sub.BB line l3 and its gate connected to a V.sub.CC line l1 via the capacitor C.sub.A. The supply voltage V.sub.CC and the the ground voltage V.sub.SS are applied to the V.sub.CC line l1 and V.sub.SS line l2, respectively, and a negative substrate bias voltage V.sub.BB from the V.sub.BB generating circuit 12 is applied to the V.sub.BB line l3. The transistor Q.sub.2 has its drain connected to the gate of the transistor Q.sub.1 via a node P.sub. 1 and its source connected to the V.sub.BB line l3. Moreover, the gate of the transistor Q.sub.2 is provided with the output signal POR of the POR pulse generating circuit 14. Parasitic capacitance C.sub.T lies between the Vcc line l1 and the V.sub.BB line l3.
FIG. 5 illustrates an example of the circuit configuration of the POR pulse generating circuit 14 shown in FIG. 4. This circuit configuration shown in FIG. 5 is disclosed in Japanese Patent Laying Open No. 61-222318. As illustrated in the figure, the POR pulse generating circuit of FIG. 5 is formed of P-channel MOS transistors Q.sub.3, Q.sub.5, Q.sub.7, Q.sub.8, N-channel MOS transistors Q.sub.4, Q.sub.6, a resistor R, a capacitor C.sub.1 and a diode D. In this POR pulse generating circuit, the output POR is at a low level in a given time period after the supply voltage is applied; however, when a charge is stored in the capacitor C.sub.1 in a given time period and the potential of node P.sub.2 exceeds a threshold of an inverter comprising the transistors Q.sub.3 and Q.sub.4, the output POR goes to a high level and is kept at the high level thereafter.
The operation of a conventional circuit in FIG. 4 will now be described in reference with a timing chart illustrated in FIG. 6A. FIG. 6A illustrates changes of the supply voltage V.sub.CC dependent on the time elapsed, the potential V.sub.P1 of the node P.sub.1, the POR signal and the substrate voltage V.sub.BB immediately after the supply voltage V.sub.CC is applied. As the supply voltage V.sub.CC rises, the potential V.sub.P1 of the node P.sub.1 also rises due to capacitive coupling of the capacitor C.sub.A. Further, the substrate voltage V.sub.BB also rises due to capacitive coupling of the parasitic capacitor C.sub.T ; however, when the potential V.sub.P1 of the node P.sub.1 exceeds the threshold of the transistor Q.sub.1, the transistor comes to be conductive, and the line V.sub.SS line l2 and V.sub.BB line l3 are short-circuited, so that the substrate voltage V.sub.BB is forced to be clamped to 0 V. Subsequently, as a given time elapses after the supply voltage is applied, the signal POR goes to a high level and the transistor Q.sub..sub.2 comes to be conductive, so that the potential of the node P.sub.1 is discharged to 0 V. As a result, the transistor Q.sub..sub.1 comes to be conductive. Subsequently, the substrate voltage V.sub.BB proceeds in a negative direction to be stable through the operation of the V.sub.BB generating circuit 12. As described heretofore, the substrate voltage is forced to be clamped to 0 V so as to prevent latch up within a given time period after the supply voltage is applied, in a conventional example in which the V.sub.BB clamping circuit 13 is in use.
FIG. 7 illustrates an input circuit of an external row address strobe signal (hereinafter referred to as an Ext.multidot.RAS signal) of DRAM (dynamic random access memory) disclosed, for example, in Japanese Patent Laying Open No. 63-10397. The conventional example of FIG. 7 is formed of an input prohibiting circuit 15 and a POR pulse generating circuit 16. The input prohibiting circuit 15 is formed of a P-channel MOS transistor Q.sub.10 and an N- channel MOS transistor Q.sub.11, comprising a CMOS inverter for producing an internal row address strobe signal (hereinafter referred to as an Int.multidot.RAS signal) inverted from the Ext.multidot.RAS signal, and a P-channel MOS transistor Q.sub.9 and an N-channel MOS transistor Q.sub.12 for prohibiting the output operation of this CMOS inverter The POR pulse generating circuit 16 comprises a resistor R, a capacitor C.sub.2, a P-channel MOS transistor Q.sub.13 and an N-channel MOS transistor Q.sub.14, outputting a signal POR for defining an input prohibiting operational timing of the input prohibiting circuit 15. The POR pulse generating circuit 16 performs the same operation as the one in which the transistors Q.sub.5 and Q.sub.6 are removed from the POR pulse generating circuit shown in FIG. 5. That is, after the supply voltage is applied, the POR pulse generating circuit 16 generates such a pulse signal POR as to be at a high level equal to the supply voltage V.sub.CC within a given time period, but fall down to a low level after the given time period. The Int.multidot.RAS signal produced in the input prohibiting circuit 15 is supplied to a main circuit of the semiconductor integrated circuit device via an input circuit 17. The input circuit 17 comprises, for example, a latch and a timing generator.
Now, the operation of the input circuit of the Ext.multidot.RAS signal in DRAM shown in FIG. 7 will be described in reference to a timing chart illustrated in FIG. 8A. FIG. 8A illustrates changes of the supply voltage V.sub.CC depending on the time elapsed, the Ext.multidot.RAS signal, the Int.multidot.RAS signal and the POR signal when the supply voltage V.sub.CC is applied. Even if the Ext.multidot.RAS signal is already at a low level before the supply voltage is applied, the transistor Q.sub.9 is rendered non-conductive and the transistor Q.sub.12 conductive because the POR signal goes to a high level as the supply voltage rises, so that the input prohibiting circuit 15 makes the Int.multidot.RAS signal be at a low level (non-active state) despite the state of the Ext.multidot.RAS signal Accordingly, activation of the Int.multidot.RAS signal is prohibited so that the main circuit is inoperative. When the POR signal goes down to a low level after a given time has elapsed thereafter, the transistor Q.sub.9 is rendered conductive while the transistor Q.sub.12 non-conductive, so that the Int.multidot.RAS signal inverted from the Ext.multidot.RAS signal is transmitted to the input circuit 17 so as to start the operation of the main circuit. As described above, the operation of the main circuit in a given time is prohibited after the supplied voltage is applied in the conventional example shown in FIG. 7. Therefore, the substrate voltage V.sub.BB does not rise in a given time, resulting from the start of operation of a sense amplifier included in the main circuit, so that latch up is prevented when a power supply is turned on.
As mentioned above, the conventional semiconductor integrated circuit device has a problem of causing latch up when the supply voltage rises sharply as described hereinafter, although preventing the latch up when the power supply is turned on.
First of all, in the conventional example shown in FIG. 4, when the supply voltage Vcc rises sharply as shown in FIG. 6B, the signal POR rises rapidly, so that clamping operation by the V.sub.BB clamping circuit 13 is ended before the rising of the supply voltage V.sub.CC is completed (at time t1). However, since the supply voltage V.sub.CC is still low at this time t1, the driving capability of the V.sub.BB generating circuit 12 is also low. Consequently, a rise in the substrate voltage V.sub.BB after the time t1 when the clamping operation is completed. At this time, if the main circuit starts operating responsive to an external signal, electric currents flow in the semiconductor substrate so as to cause fluctuation of the substrate voltage V.sub.BB. The prompt fluctuation of the substrate voltage V.sub.BB in a positive direction causes latch up.
In addition, in the conventional example shown in FIG. 7, if the supply voltage V.sub.CC rises sharply as shown in FIG. 8, a falling timing of the signal POR is early, so that the main circuit starts operating before the supply voltage V.sub.CC sufficiently rises (at time t3). At this time, since the driving capability of the V.sub.BB generating circuit is still low, the substrate voltage happens to fluctuate greatly after the time t3 due to the operation of the main circuit so as to cause the latch up.